Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows the material's electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support, electrical interconnect, and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
One approach to achieving the objectives of greater integration and smaller semiconductor devices is to focus on three-dimensional (3D) packaging technologies including package-on-package (PoP). The manufacturing of smaller semiconductor devices relies on implementing improvements to horizontal and vertical electrical interconnection between multiple semiconductor devices on multiple levels, i.e., 3D device integration. A reduced package profile is of particular importance for packaging in the cellular or smart phone industry. However, PoP devices often require laser drilling to form vertical interconnect structures, e.g., through mold vias, which increases equipment costs and requires drilling through an entire package thickness. Laser drilling increases cycle time (CT) and decreases manufacturing throughput. Vertical interconnections formed exclusively by a laser drilling process can result in reduced control and design flexibility. Furthermore, conductive materials used for forming through mold vias within a PoP, can be incidentally transferred to semiconductor die during package formation, thereby contaminating the semiconductor die within the package.
A semiconductor die can be tested to be a known good die (KGD) prior to mounting in a semiconductor package, e.g., a fan-out wafer level chip scale package (Fo-WLCSP). The semiconductor package can still fail due to defects in the build-up interconnect structure, causing loss of the KGD. Lower yield is expected for WLCSP with dual side fan-out build-up interconnect structures. A semiconductor package size greater than 10 by 10 millimeter (mm) with fine line spacing and multilayer structures is particularly susceptible to defects in the build-up interconnect structure. When the WLCSP with dual side fan-out build-up interconnect structures includes a larger die, the expected yield is lower yet, further increasing the loss of KGD.
Additionally, electrical connection between stacked semiconductor devices often requires first and second side redistribution layers (RDLs) to be formed over opposing surfaces of the semiconductor die. In the manufacture of semiconductor packages having first and second side RDLs, semiconductor die are often mounted to a first temporary carrier and an encapsulant is deposited over the semiconductor die and first carrier to form a reconstituted panel or reconfigured wafer. A first side redistribution interconnect structure is formed over the semiconductor die and encapsulant. The workpiece is inverted and mounted to a second temporary carrier, increasing cost. The first temporary carrier is then removed. Total thickness variation (TTV) in temporary bonding and debonding is a challenge due to the warpage of fanout substrate, especially after one side RDL process. A second side redistribution interconnect structure is formed over the semiconductor die and encapsulant. The first temporary carrier is then removed. The reconstituted panel is bumped and diced. However, flaws in the manufacturing process of either the first side redistribution interconnect structure or second side redistribution interconnect structure cause reduced yield and increased loss of KGD. Additionally, the CT of known methods of manufacture of semiconductor packages having first and second side RDLs manufactured on a single production line is too long to support today's demands to fulfill customer orders with minimal inventory. Maintaining inventory causes waste, as stored inventory rapidly becomes un-sellable out of date product.